This application claims the benefit of Korean Patent Application No. 2000-46232, filed on Aug. 9, 2000, under 35 U.S.C. xc2xa7119, the entirety of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to an apparatus and a method for a burn-in test in semiconductor device, and more specifically for a package level burn-in test.
2. Description of Related Art
It is important to test mass produced semiconductor memory chips before using them. But it takes too much time to test their normal operation life span in their expected normal surroundings. Therefore, it is desired to test in a way that uses reduced test time, so as to predict their life span.
This is accomplished by a burn-in test. The burn-in test is a method that applies excess stresses to chips in a short period in worse surroundings than the expected normal surroundings. Then life spans of chips in actual operation surroundings are guaranteed for only those products that had passed such stress tests.
Burn-in tests are preformed more efficiently, as wafer level burn-in tests. Those include not only DC voltage tests, but sensing and writing operation tests, which are effective in screening out bad chips.
FIG. 1 is a configuration illustrating a conventional wafer level burn-in test circuit. The chips of a wafer are divided by scribe lines. One of them is placed in the test circuit.
The test circuit includes a burn-in test circuit 10, and dummy pad unit 20 for receiving various types of test voltages.
After receiving a wafer burn-in enable signal WBE, the wafer burn-in circuit 10 generates a master test signal PWBE. At this point, the wafer burn-in circuit 10 receives test voltages VPP, VBB, VP, and VBL through dummy pad unit 20 from the outside, to provide a stable DC supply. In addition, the wafer burn-in circuit 10 receives various test control signals through address pads A0 to A5 for the burn-in test.
A problem in the prior art is that the above described arrangement can perform a burn-in test only in a wafer state, but not in a package state. That is because the dummy pad unit 20 cannot be connected to the outside in the package state.
Therefore, many studies for package level burn-in test have been done. The U.S. Pat. Nos. 5,471,429 and 5,638,331 disclose circuits and methods for package level burn-in tests. However, they work only by using fuses, which limits the burn-in test from being performed once only. That is because an automated process must be halted to replace them.
To overcome the above-described problems, the present invention provides an apparatus and a method for a package level burn-in test in semiconductor devices.
The apparatus includes a package burn-in register, a test voltage generator for the package level burn-in test, a burn-in master signal generator, and a burn-in test circuit. The package burn-in register stores a package burn-in set-order from the outside and generates a package burn-in set-signal. The test voltage generator generates burn-in test voltages in response to the package burn-in set-signal and to address signals through first address terminals from the outside. The burn-in master signal generator generates a burn-in master signal by combining and receiving the second address signal form first address terminals, a wafer burn-in enable signal from a control signal input terminal, and the package burn-in set-signal. After receiving the burn-in master signal, multiple address signals from multiple third address terminals, and the test voltages for the package level burn-in test, the burn-in test circuit performs a package level burn-in test.
Therefore, by receiving test voltages and test control signals required in a burn-in test, the present invention performs a package level burn-in test in the same method of a wafer level burn-in test. No fuses are needed, or their time to replace them after each time they burn out.